IxVerify vs Mentor Graphics MODELSIM comparison

IxVerify provides hundreds of predefined packet templates for testing Ethernet and TCP/IP protocols and is capable of generating high volumes of traffic. With its ability to run hundreds of virtualized test ports at once, it offers the unique ability to dynamically shape traffic to ensure zero packet loss at maximum emulation speeds.

• Validates networking chip design earlier in the development cycle
• Generates custom Ethernet traffic by using predefined packet templates
• Delivers powerful statistics with bandwidth analysis and latency measurements
• Offers dynamic traffic rate shaping for zero packet loss
• Shares test configurations with IxNetwork VE
• Provides test automation via multiple languages, including REST API
• Provides flexible test environment definition with support for multiple users
• Enables faster time to market for next generation networking chips

In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.

The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).