In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.
The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
Mentor Graphics MODELSIM is ranked 1st in Electronic Design Automation while Synopsys Saber is ranked 3rd in Electronic Design Automation. Mentor Graphics MODELSIM is rated 0.0, while Synopsys Saber is rated 0.0. On the other hand, Mentor Graphics MODELSIM is most compared with Cadence Incisive Palladium and Mentor Graphics PADS, whereas Synopsys Saber is most compared with Cadence Incisive Palladium and Mentor Graphics PADS.
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